The field of art to which this invention relates is electronic packaging. More specifically, the present invention relates to a method and apparatus for assembling a conformal chip carrier to a flip chip.
Typically, one or more semiconductor chips, or other such electronic devices, are mounted on a first circuitized substrate (called a semiconductor chip carrier, or more generally, a first level electronic package), which, in turn, is mounted on a second circuitized substrate such as a printed circuit card or board (more generally called a second level electronic package). The electronic devices mounted on the first level electronic package are electrically connected through the circuitry of the first level package to the circuitry of the second electronic package. The resulting structure may be used as part of a computer or other such equipment.
A particularly versatile first level electronic package is a flexible film, or conformal, semiconductor chip carrier. This type of first level electronic package comprises a circuitized flexible substrate and having circuitry formed on at least one side. A semiconductor chip, or other such electronic device, may be mounted on pads, such as controlled collapse chip connection (C4) pads, which are part of the circuitry formed on the flexible substrate. Conventional techniques are used to mount the flexible film chip carrier to the semiconductor chip. One such technique is called solder reflow which uses solder bumps, such as C4 solder balls corresponding to the C4 pads. With each contact pad on the chip carrier being positioned on the appropriate solder bump on the chip, the assembly is heated so as to liquefy the solder and bond each contact pad on the chip carrier to the confronting solder bump on the chip.
Conformal chip carriers are very difficult to assemble a flip chip to. The reason being is the organic substrate from which the chip carrier is fabricated, is very soft due to the dielectric being a thermal plastic (no polymer cross linking), being filled with silica particles, and not having glass cloth for stiffness. The problem arises when a flip chip is placed on top of a compliant structure and thermal cycled during solder reflow. The chip remains rigid but the compliant structure sags or bows during the thermal cycling causing it to separate or detach from the solder bumps on the chip surface. This separation causes opens between the chip and the organic carrier. This problem is magnified as the chip size and the number of C4 solder balls on the chip increase.
More traditional organic chip carriers have been made out of epoxy (thermal set with polymer cross linking) and woven glass dielectrics which makes the total structure of the chip carrier and chip rigid. Thus, when the chip is placed onto the organic structure and thermal cycled during solder reflow the chip carrier does not pull away from the chip. However, these traditional chip carriers are for low temperature reflow and cannot be used with the high temperature reflows associated with C4 techniques.
Another approach to the problem of chip carrier separation during reflow has been to attach a metal stiffener (a xe2x80x9cpicture framexe2x80x9d) to the conformal organic chip carrier with adhesives prior to chip attachment. This approach helps to some extent, but z-axis (sag or bow) movement still occurs in the chip area which will create opens. Another problem is that the adhesive used, limits the reflow temperatures allowed or would require new adhesives to be developed which would be able to withstand higher temperatures..
Yet another approach to the problem is to stretch the chip carrier taut. This is accomplished by pulling the carrier on four corners and holding it in tension during the reflow process. This requires additional room on the carrier for tooling holes and has only been done on flexible polyimide carriers at traditional reflow temperatures (i.e., peak temperatures of 220xc2x0 C.).
Furthermore, alignment of the chip carrier with the chip can be done with manual split field optical systems to view the ball surface of the chip and the pad surface of the chip carrier so that both can be aligned, or with fully automated and costly in-line advanced placement tools. This is a necessary step in the packaging processes of the prior art. However, the alignment of the balls with the pads does not have to be perfect, because of the inherent self-alignment properties of the C4 techniques. If the ball is contacting any portion of a corresponding pad, the ball will self-align with the pad. However, the prior art methods for attaching a conformal chip carrier to a flip chip do not take full advantage of this self-aligning feature because of the configuration of the chip relative to the chip carrier during reflow.
Therefore, there is a need in the art for a method and apparatus for attaching a conformal chip carrier to a chip, such as a flip chip, which eliminates sagging or bowing of the chip carrier during reflow, and thus eliminates opens, resulting in increased yields. In addition, there is a need in the art for a method and apparatus which takes advantage of the self-alignment properties of the C4 process and one which eases the alignment and attachment of complex chip patterns to conformal chip carriers.
Therefore, it is an object of the present invention to provide an apparatus and method for attaching a conformal chip carrier to a semiconductor chip which prevents the chip carrier from separating from the chip surface.
It is yet another object of the present invention to provide an apparatus and method for attaching a conformal chip carrier to a semiconductor chip which obviates the need for a rigid chip carrier structure.
It is yet another object of the present invention to provide an apparatus and method for attaching a conformal chip carrier to a semiconductor chip which eliminates the need for stiffener attachments to the conformal chip carriers during solder reflow.
It is yet another object of the present invention to provide an apparatus and method for attaching a conformal chip carrier to a semiconductor chip which is compatible with both low temperature reflow and C4 reflow.
It is yet another object of the present invention to provide an apparatus and method for attaching a conformal chip carrier to a semiconductor chip which takes advantage of the self-aligning characteristics of C4 solder balls.
It is still yet another object of the present invention to provide an apparatus and method for attaching a conformal chip carrier to a semiconductor chip which eliminates the need for costly and complicated alignment systems.
Accordingly, a first embodiment of a fixture for attaching a semiconductor chip to a substrate is disclosed. The semiconductor chip has an array of joining material bumps. The substrate has an array of conductive pads corresponding to the array of joining material bumps. The fixture has a body having a first cavity for containing the semiconductor chip and a second cavity in communication with the first cavity for containing the substrate. The substrate is placed over the semiconductor chip with the conductive pads opposing and in contact with the joining material bumps, such that during reflow of the joining material bumps, the weight of the substrate acts against the joining material bumps and aids in the attachment of the semiconductor chip to the substrate to form electrical connections therebetween. The dimensions of the first and second cavities preferably have tolerances such that upon holding of the tolerances, the joining material bumps are ensured to line up with at least an edge of the conductive pads thus eliminating the need for alignment systems.
A second embodiment of a fixture for attaching the semiconductor chip to the substrate is also disclosed. The fixture comprises a first plate having a first opening for disposal of the semiconductor chip therein, a second plate stacked below the first plate and having a thickness substantially equal to the thickness of the substrate, the second plate further having a second opening opposing the first opening for disposal of the substrate therein, and a third plate stacked below the second plate such that the substrate is flattened in the second opening under the weight of the first plate thereby aiding in the attachment of the joining material bumps to their corresponding conductive pads during solder reflow to form electrical connections therebetween.
Also disclosed are methods for attaching the semiconductor chip to the substrate using the fixtures of the present invention.
In a preferred embodiment of both the apparatus and method of the present invention, the joining material bumps are solder balls attached to the semiconductor chip in accordance with a C4 process and the substrate is a conformal chip carrier.
These and other features, aspects, and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
FIG. 1 illustrates a top, or plan view, of a first embodiment of the fixture of the present invention.
FIG. 2A illustrates a sectional view of the fixture of FIG. 1 taken about line 2Axe2x80x942A.
FIG. 2B illustrates the sectional view of FIG. 2A with the chip, chip carrier, and weight disposed therein.
FIG. 3 illustrates a partial sectional view of the fixture of FIG. 2 showing the relationship of the conductive pad relative with the solder ball before reflow.
FIG. 4 illustrates a partial sectional view of the fixture of FIG. 2 showing the relationship of the conductive pad relative with the solder ball after reflow.
FIG. 5 illustrates a flow chart outlining the steps of a method of the present invention which utilizes the first embodiment of the fixture of the present invention.
FIG. 6 illustrates a sectional view of a second embodiment of the fixture of the present invention.
FIG. 7A illustrates a plan view of the top plate of the fixture of FIG. 6.
FIG. 7B illustrates a plan view of the middle plate of the fixture of FIG. 6.
FIG. 7C illustrates a plan view of the bottom plate of the fixture of FIG. 6.
FIG. 8 illustrates a flow chart outlining the steps of a method of the present invention which utilizes the second embodiment of the fixture of the present invention.